1. Field of the Invention
The present invention relates to the fabrication of integrated circuit, and more particularly, to a method of improving the gap filling characteristics of dielectric layer and forming void-free dielectric layer.
2. Description of the Prior Art
In the fabrication of integrated circuit, dielectric materials are employed in many applications such as covering semiconductor structures, forming passivation layer and forming isolation layer. In specially, when packing density of integrated circuit is increased and multi-layer structure is required, dielectric materials are employed to separate alternate layers and then some structures such as inter metal dielectric (IMD) and inter layer dielectrics (ILD) are formed.
In general, dielectric material is formed over a surface that some semiconductor structures are located in and on it. Obviously, not only these semiconductor structures are covered by dielectric layer but also these gaps that locate between portions of semiconductor structures are filled by dielectric layer. No matter how, the formation of dielectric layer is subject to arrival angle effect and shadowing effect. That is, the forming rate of dielectric is faster in the corner region of said semiconductor structures than other regions of said semiconductor structures. Thus, there are voids inside dielectric layer and the density of voids are direct proportion to aspect of said gaps.
FIG. 1A to FIG. 1C illustrate the formation of voids. First, as shown in FIG. 1A, the top surface 11 of semiconductor substrate 10 is planarized and a plurality of semiconductor devices are formed in and on semiconductor substrate 10. Then a plurality of semiconductor structures 12 are formed on top surface 11 and there are gaps 13 between portions of semiconductor structures 12. Second, a first dielectric layer 14 is formed over the top surface 11 and then semiconductor structures 12 are covered by it. Obviously, as FIG. 1B shows, when the aspect of gap 13 is small then only overhangs 15 are formed in the corner parts of semiconductor structures 12, but when the aspect of gap 13 is large then there is void 16 inside gap 13. Third, second dielectric layer 17 is sequentially formed over first dielectric layer 14, where possible material of second dielectric layer 17 comprises material of first dielectric layer 14. Obviously, as shown in FIG. 1C, not only the top surface of second dielectric layer 17 is non-uniform where dips 18 are located above the gaps 13 but also there are voids 16 inside the second dielectric layer and the location of voids 16 correspond to the location of gap 13.
According to the previous discussion, it is obvious that when aspect of gap 13 is large enough, there are voids 16 within the gap 13 or above the gap 13 and the quality of the integrated circuit is degraded by these voids 16. Thus, it is desired to find a gap filling technique that will fill a gap without the presence of any void and then the formed integrated circuit is void-free.